1. Field of the Invention
The embodiments of present invention discussed herein relate to a method of manufacturing a silicon carbide semiconductor device.
2. Description of the Related Art
A silicon carbide (SiC) semiconductor has a dielectric breakdown field strength about 10 times higher than conventional semiconductor materials such as a silicon (Si) semiconductor and a gallium arsenide (GaAs) semiconductor, and also has high thermal conductivity. Therefore, silicon carbide semiconductors have recently attracted attention as a semiconductor material enabling production (manufacturing) of a metal oxide semiconductor field effect transistor (MOSFET) for a power device enabling both maintenance of breakdown voltage and reductions in size.
In general, main contributors to energy loss during operation of a MOSFET include drift resistance (a resistance component of a drift layer), channel resistance (a resistance component of an inversion layer (channel) formed in a base region), and contact resistance (an electrical contact resistance component of a semiconductor device region and a metal electrode). Among these resistance components, contact resistance must be sufficiently reduced as compared to the drift resistance and the channel resistance. Even when a semiconductor device that employs a silicon carbide semiconductor (hereinafter, silicon carbide semiconductor device) is produced (manufactured), formation of an ohmic contact with a metal electrode poses a technical problem.
The ohmic contact between a silicon carbide semiconductor device region and a metal electrode is conventionally formed by using a method for forming a contact between a silicon semiconductor device region and a metal electrode to convert a metal film of nickel (Ni), titanium (Ti), etc. formed on a surface of the semiconductor device region into a silicide by annealing (heat treatment). For example, the contact resistance of an n-type silicon carbide semiconductor device region and a metal electrode obtained by this method is about 10−4 Ωcm2, which is sufficiently smaller as compared to the channel resistance. A method of forming a contact has also been disclosed with respect to a case of using, as a semiconductor material, strontium titanate (SrTiO3) doped with niobium (Nb), which like a silicon carbide semiconductor, has a large bandgap of 3.2 eV.
In a proposed method of manufacturing a semiconductor device using Nb-doped SrTiO3, a dipole is formed at a junction interface of an Nb-doped SrTiO3 layer and a Strontium Ruthenate (SrRuO3) film, which is a metal oxide film, by disposing at the junction interface, a lanthanum oxide (LaO) layer that is more positively charged than the SrO film, whereby a Schottky barrier is decreased (for example, refer to Yajima, T., et al, “Controlling Band Alignments by Engineering Interface Dipoles at Perovskite Oxide Heterointerfaces”, Photon Factory News, High Energy Accelerator Research Organization, February 2012, Vol. 29, No. 4, pp. 13 to 16). In “Controlling Band Alignments by Engineering Interface Dipoles at Perovskite Oxide Heterointerfaces”, Yajima, T., et al describe that characteristics of an interface of one (single-layer) semiconductor layer and a metal film can be controlled by a dipole formed at the interface. In other words, this is a method of control enabling interface characteristics that exceed the characteristics of a junction interface of a semiconductor device region and a metal electrode formed by simply depositing the metal electrode on the semiconductor device region.
In other proposed methods of manufacturing a silicon carbide semiconductor device, graphene (a sheet-like substance of carbon atoms bound into a hexagonal lattice pattern with a thickness of one carbon atom) is used for forming an electrode (for example, refer to Japanese Laid-Open Patent Publication Nos. 2012-190982, 2011-096905, and 2013-187420; Tadjer, M. J., et al, “Vertical conduction mechanism of the epitaxial graphene/n-type 4H-SiC heterojunction at cryogenic temperatures”, Applied Physics Letters, USA, American Institute of Physics, 2012, Vol. 100, No. 193506; and Hertel, S., et al, “Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics”, Nature Communications, U.K., Macmillan Publishers, 2012.7.17, Vol. 3, No. 957). Japanese Laid-Open Patent Publication No. 2012-190982 (paragraphs 0023 to 0024 and 0037) discloses that graphene is used for a source electrode and a drain electrode of a silicon carbide MOSFET. In Japanese Laid-Open Patent Publication No. 2012-190982, a metal film or a carbon (C) film is deposited on a silicon carbide semiconductor device region and the silicon carbide semiconductor device region is reacted with the metal film or the carbon film by an anneal contact to form the source electrode and the drain electrode.
Japanese Laid-Open Patent Publication No. 2011-096905 discloses that a carbon (C) layer and a metal layer are deposited sequentially on a silicon carbide semiconductor device region and that the metal layer is caused to react with the silicon carbide semiconductor device region and the carbon layer by an anneal contact to form an ohmic contact having low contact resistance. Japanese Laid-Open Patent Publication No. 2013-187420 (paragraphs 0061 to 0068) discloses that a carbon layer and a tantalum (Ta) layer are formed sequentially on a C plane of a silicon carbide semiconductor substrate and that the carbon layer is caused to react with the tantalum layer by a heat treatment to form an ohmic contact of tantalum carbide (TaC). Japanese Laid-Open Patent Publication No. 2011-096905 (paragraph 0063) and Japanese Laid-Open Patent Publication No. 2013-187420 (paragraph 0071) disclose that graphene is used as the carbon layer.